In addition to Fast Lint , the company will be demonstrating hierarchical analysis support, which abstracts design elements that have been pre-analyzed for higher chip-level analysis. This approach can deliver 5X to over an order-of-magnitude speed improvement for highly complex designs as compared to running flat i. The SpyGlass linting solution analyzes a design at the register transfer level RTL of abstraction for coding styles and circuit constructs that can cause verification and implementation issues. Linting forms the base capability for the SpyGlass platform, which is also used widely for power optimization, clock synchronization verification CDC , testability, constraints management and routing congestion analysis. Design groups use SpyGlass to verify that their design is ready to be handed off to back-end physical implementation tools. It is also used by revision control systems before new code check-in occurs.

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The solution not only detects, but can also automatically fix key power management issues. The SpyGlass-Power solution supports UPF and CPF power formats and verifies designs with voltage and power domain management structures so that voltage level shifters and isolation logic are correct.

The SpyGlass-DFT solution not only detects testability issues -- it can also automatically correct them. We are very pleased with the SpyGlass results on our chip designs. Customers benefit from Atrenta tools and methodologies to capture design intent, explore implementation alternatives, validate RTL and optimize designs early, before expensive and time-consuming detailed implementation.

For more information, visit www. Atrenta, Right from the Start! All others are the property of their respective holders. This press release contains forward-looking statements. Atrenta disclaims any obligation and does not undertake to update or revise the forward-looking statements in this press release. Atrenta Corporate: Atrenta Inc. Contacts Atrenta Corporate: Atrenta Inc. Log In Sign Up.


Atrenta Introduces Fast Lint for SpyGlass®

To address this growing complexity, FPGA vendors like Xilinx are providing more and more IP blocks for standard functions to maximize design reuse, lower power, and improve efficiency. A significant share of these IP is delivered to customers either encrypted or as hardened macros by Xilinx. Traditionally, 3 rd party EDA tools for RTL analysis and verification have treated these as black boxes for lack of visibility into the internals. This approach can be error-prone, especially for CDC verification where it is essential to trace all paths leading into and out of these IP. Atrenta has collaborated with Xilinx to add support for these blocks seamlessly in SpyGlass using IEEE encryption and also leveraging industry standard models for hard macros. This collaboration with Xilinx will benefit our mutual customers in utilizing the full potential of the industry leading CDC solution.


Atrenta's SpyGlass SoC Addresses Logic Integration Issues that Plague IC Design Efforts

Accelerating 5G virtual RAN deployment. RoT: The Foundation of Security. Managing connected devices at scale: Connect millions of shipments on one platform. Arm Mali Best Practices 2.

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