Traditionally, industrial delta-sigma ADCs offering. As a result, they have limited signal. High-resolution ADCs in audio. The ADS The high-order, chopper-stabilized modulator.
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IC datasheet pdf-ADS IC datasheet pdf-TLV IC datasheet pdf-PCM The devices are offered in identical packages, permitting drop-in expandability. Traditionally, industrial delta-sigma ADCs offering good drift performance use digital filters with large passband droop. As a result, they have limited signal bandwidth and are mostly suited for dc measurements. High-resolution ADCs in audio applications offer larger usable bandwidths, but the offset and drift specifications are significantly weaker than respective industrial counterparts.
The ADS and ADS combine these types of converters, allowing high-precision industrial measurement with excellent dc and ac specifications.
The high-order, chopper-stabilized modulator achieves very low drift with low in-band noise. The onboard decimation filter suppresses modulator and signal out-of-band noise. Four operating modes allow for optimization of speed, resolution, and power.
All operations are controlled directly by pins; there are no registers to program. DC Accuracy: 0. Linear Phase Digital Filter? Low Sampling Aperture Error? Modulator Output Option digital filter bypass? Analog Supply: 5V? Digital Core: 1. SPI is a trademark of Motorola, Inc. All other trademarks are the property of their respective owners. Products conform to specifications per the terms of the Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
Exposure to absolute maximum conditions for extended periods may degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those specified is not implied. V, rms? Best fit method. A MHz MHz 0. THD includes the first nine harmonics of the input signal; Low-Speed mode includes the first five harmonics.
The inputs may float. AINP Positive analog input, channels 4 through 1. Synchronize input all channels. PWDN Power-down control for channels 4 through 1. Frame-Sync protocol: frame clock input; SPI protocol: data ready output. Digital core power supply. DOUT Data output for channels 4 through 1. Analog power supply 4. Negative reference input.
Positive reference input. Master clock input fCLK. CLK input divider control: Digital ground power supply. Daisy-chain data input. AINN Negative analog input, channels 4 through 1. Figure 6. Figure They offer the combination of outstanding dc accuracy and superior ac performance. Figure 57 shows the block diagram. The packages are identical, and the ADS pinout is compatible with the ADS, permitting true drop-in expandability. The converters are comprised of four ADS or eight ADS advanced, 6th-order, chopper-stabilized, delta-sigma modulators followed by low-ripple, linear phase FIR filters.
The digital filters receive the modulator signal and provide a low-noise digital output. Table 1 summarizes the performance of each mode. The digital filters can be bypassed, enabling direct access to the modulator output. VRMS 8. Submit Documentation Feedback Copyright? The converter is composed of two main functional blocks to perform the ADC conversions: the modulator and the digital filter.
The modulator samples the input signal together with sampling the reference voltage to produce a 1s density output stream. The density of the output stream is proportional to the analog input level relative to the reference voltage. The pulse stream is filtered by the internal digital filter where the output conversion result is produced.
In operation, the input signal is sampled by the modulator at a high rate typically 64x higher than the final output data rate. The quantization noise of the modulator is moved to a higher frequency range where the internal digital filter removes it. Oversampling results in very low levels of noise within the signal passband. Since the input signal is sampled at a very high rate, input signal aliasing does not occur until the input signal frequency is at the modulator sampling rate.
This architecture greatly relaxes the requirement of external antialiasing filters because of the high modulator sampling rate. Furthermore, the digital filters are synchronized to start the convolution phase at the same modulator clock cycle. The phase match of one 4-channel ADS to that of another ADS eight or more channels total may not have the same degree of sampling match.
As a result of manufacturing variations, differences in internal propagation delay of the internal CLK signal coupled with differences of the arrival of the external CLK signal to each device may cause larger sampling match errors.
Equal length CLK traces or external clock distribution devices can be used to reduce the sampling match error between devices. The filter uses a multi-stage FIR topology to provide linear phase with minimal passband ripple and high stop band attenuation. The filter coefficients are identical to the coefficients used in the ADS Table 2. The CLK input controls the timing of the modulator sampling instant.
The converter is designed such that the sampling skew, or modulator sampling aperture match between channels, is Copyright? Figure 59 shows the passband ripple. The transition from passband to stop band is shown in Figure The overall frequency response repeats at 64x multiples of the modulator frequency fMOD, as shown in Figure Often, a simple RC filter is sufficient.
Table 3 lists the image rejection versus external filter order. Table 3. Figure 63 shows the passband ripple, and the transition from passband to stop band is shown in Figure Frequency Response for High-Resolution Mode 0. Linear phase filters exhibit constant delay time versus input frequency constant group delay.
This characteristic means the time delay from any instant of the input signal to the same instant of the output data is constant and is independent of input signal frequency. This behavior results in essentially zero phase errors when analyzing multi-tone signals.
Table 4. Figure 66 shows the output settling behavior after a step change on the analog inputs normalized to conversion periods. The X-axis is given in units of conversion. Note that after the step change on the input occurs, the output data change very little prior to 30 conversion periods. The output data are fully settled after 76 conversion periods for High-Speed and Low-Power modes, and 78 conversion periods for High-Resolution mode. Likewise, the most negative measurable differential input is —VREF, which produces the most negative digital output code of h.
Fixing the input to 2. The range for this voltage is: —0. If these conditions are possible, external Schottky clamp diodes or series resistors may be required to limit the input current to safe values see the Absolute Maximum Ratings table. See the Application Information section for several recommended circuits.
A positive full-scale input produces an ideal output code of 7FFFFFh, and the negative full-scale input produces an ideal output code of h. The output clips at these codes for signals exceeding full-scale. Table 4 summarizes the ideal output codes for different input signals.
Datasheet Texas Instruments ADS1274
ADS1274 Converters. Datasheet pdf. Equivalent